This invention relates to a semiconductor integrated circuit device and, more specifically, to a semiconductor integrated circuit device comprising a plurality of well regions of the same conductivity type by providing a well region in the semiconductor substrate and providing an isolation trench extending inwardly from the well region surface the above semiconductor substrate and in particular, relates to an especially effective technology applicable to a semiconductor memory device having memory cells formed in a plurality of isolated well regions of the same conductivity type and having at least one isolated well region to which there is applied a voltage different from other well regions.
According to technology for forming a plurality of circuit blocks or devices on the well on a semiconductor substrate in high density and also isolating the circuit blocks and devices securely, the technology of providing a well with an isolation trench extending from the well surface to the above substrate is known. In a semiconductor integrated circuit device of this type, the electrically-erasable-programmable programmable read only memory (EEPROM), which was invented by the present inventors, is known as shown in Japanese Patent Laid-Open No. 61-281546.
In the above EEPROM, many memory cells are formed in wells of the same conductivity type which are isolated by trenches in the semiconductor substrate, and are composed such that individual memory cell groups which consist of a specified number of memory cells are respectively isolated from each other by surrounding each well with isolation trenches so as to enable the erase, write and read of information with respect to every specified number of memory cells (for example, every byte).
According to an experiment by the present inventors, although the semiconductor integrated circuit device by the conventional technology mentioned above was effective for improving the integration density, processing defects occurred in the production and degradation of operating characteristics degradation was sometimes observed while such semiconductor integrated circuit device was used. The inventors further found that such problems originated from the shape of the isolation trench. In the trench isolations achieved by the conventional technology mentioned above, as shown in FIG. 19, the isolation trenches 2 surround each of the memory cell groups in the well 1, and therefore the intersection part of the isolation trenches, that is, the corner part "C", the T part "D" and the cross part are provided as shown in "C" and "D". As shown in FIG. 20, a cavity 12 develops in the filler of the isolation trench 2 and/or the stress is concentrated on the intersection part. By those reasons, a junction leak occurs as a result of such concentrated stress or mechanical destruction occurs, thereby causing a defective product and/or with a characteristics degradation.